A digital phase-locked loop (DPLL) generates an output dock that the DPLL phase locks to an input reference clock. A DPLL includes a time-to-digital converter (TDC) that generates a digital output value that is a function of the phase difference between corresponding edges of the reference clock and a feedback clock derived from the output clock. Based on the digital signal from the TDC, the output clock frequency from a voltage-controlled oscillator is adjusted to maintain phase lock.